1. Field of the Invention
The present invention relates to a dynamic random access memory (hereinafter simply referred to as DRAM), and more particularly, to a high speed DRAM with a cache.
2. Description of Related Art
High speed data transmission has been realized by incorporating a cache function into a large scale DRAM. This kind of DRAM incorporates a cache memory and a TAG memory, which generates a state flag indicating a "Hit" or "Miss" regarding data stored in the cache memory, all on an integrated circuit (IC) chip.
Related technology employing an SRAM as the cache memory is, for example, disclosed in "A Circuit Design 0f Intelligent CDRAM With Automatic Write Back Capability", pp. 79-80, 1990 Symposium on VLSI circuits digest of technical papers, June 7-9, The IEEE Solid State-Circuits Council and The Japan Society of Applied Physics, authored by K. Arimoto et al.
In this SRAM design, a TAG memory stores an X address and a Y address as a pair of TAG addresses, and the SRAM cache stores data corresponding to the TAG address. When the X address and the Y address are defined in a read operation, confirmation will be made as to whether a TAG address exists that corresponds to the X and Y addresses. If the TAG address is found in the TAG memory, that is, if there is a "hit", the corresponding data are read out from the SRAM cache at high speed.
In this manner, high speed access to stored data can be accomplished by incorporating the TAG memory and the SRAM cache into the DRAM circuit. However, this method requires use of both the X address and the Y address to map column sense amplifier data into the SRAM cache. Further, a refresh operation is performed in each memory cell sub-array. Column sense amplifier data renewed in the refresh operation do not always correspond to the TAG addresses in the TAG memory.
Moreover, an external X address or Y address is directly written into the TAG memory through a buffer circuit without performing a logic level conversion process. When the external address is directly written into the TAG memory through a buffer circuit in this manner, the TAG memory included in a large scale memory which requires stepped address decoding should be located in front of the first decoding circuit in order to avoid needlessly lengthy wiring between components. As a result, layout options are restricted for the TAG memory in a DRAM having such a configuration because the TAG memory should be located along side the Y decoder to make component connection practicable.
Moreover, when an address multiplexer type interface is employed, so that the X address and the Y address are multiplexed and transmitted, the "hit" or "miss" determination in the TAG memory cannot be performed until both the X address and the Y address are completely written to memory. Since data are read out through a memory cell (MC) after a "miss" determination, access time delay after a "miss" determination increases dramatically.
Moreover, using the SRAM cache as the cache memory necessitates an enlargement of the chip size, causing an increase in the cost to manufacture and use the chip.
To solve the above-mentioned problems, designs utilizing sense amplifiers of the DRAM circuit as the cache have been proposed. Such technology is disclosed, for example, in "To Realize 500M Bytes/sec Data Transmission Speed By 72 Bit Row Operation" pp. 75-80, August 1992, Nikkei Microdevices, authored by N. Kushiyama et al. This DRAM, which controls the sense amplifier as the cache, requires that data of the column sense amplifiers be renewed, so the corresponding addresses in the TAG memory must be purged. However, conventional DRAMs utilizing sense amplifiers as the cache have only two TAG blocks included in the TAG memory on the chip, so different TAG information cannot be stored in each of the X decoders, which may cause a decrease in the "hit" rate.
Further, the TAG memory assignment in such a DRAM corresponds to plural sub-arrays, each of which incorporates an X decoder, and the TAG memory is located in a different region in the memory array on the chip layout. A layout having these TAG blocks requires the use of lengthy bus wiring, hindering efforts to decrease the size of the TAG blocks.
As described above, a conventional DRAM structure incorporating TAG memory encounters difficulties both in reducing the chip size and in improving the hit rate.